Graf Research + Xilinx Vivado Design Suite (ML Enterprise Edition)

Enverite® PV-Bit™ software allows the end-user to ensure the FPGA bitstream implementation matches the publicly documented and formally verifiable post place-and-route simulation netlist. The application fills a gap in high assurance verification flows for security and functional safety by allowing a end-user to independently verify the functionality of the FPGA bitstream. Enverite® PV-Bit™ software evaluates the contents of the vendor-proprietary bitstream while respecting FPGA vendor IP and third-party vendor IP by performing an encapsulated comparison of the physical netlist and the bitstream.

Enverite® Trace™ archiver creates and verifies a tamper-evident auditable digital thread as a design traverses the FPGA build flow. Enverite® Trace™ archiver cryptographically signs design files, settings, and other artifacts, storing them in an archive to record the design process. Working alongside traditional vendor build flow, Enverite® Trace™ archiver captures the design, extracts the relevant implementation artifacts before and after each implementation step, and applies cryptographic hashing and signature functions as integrity verification mechanisms.

Vivado is the design software for AMD adaptive SoCs and FPGAs. It includes: Design Entry, Synthesis, Place and Route, Verification/Simulation tools. Vivado supports design entry in traditional HDL like VHDL and Verilog. The Vivado ML Edition offers two key technologies that significantly reduce design iteration times: Incremental compile and Abstract Shell. This catalog item provides the Vivado ML Enterprise Edition which support for all AMD devices. It also supports a graphical user interface-based tool called the IP Integrator (IPI) that allows for a Plug-and-Play IP Integration Design Environment.