Trusted Silicon Stratus is currently in closed beta. Please contact us if you would like to participate.

RISC-V Tools

RISC-V is an open-source hardware instruction set architecture based on established reduced instruction set computer principles.

In contrast to most ISAs, the RISC-V ISA is free and open-source and can be used royalty-free for any purpose, permitting anyone to design, manufacture and sell RISC-V chips and software. While not the first open-architecture ISA, it is significant because it is designed to be useful in a wide range of devices. The instruction set also has a substantial body of supporting software, which avoids a usual weakness of new instruction sets.

This build of RISC-V Tools contains:

  • RISC-V tools (rocket-tools a22d761 from Mar 29, 2020)
  • Rocket Chip (v1.2.6)
  • Verilator (v4.034) with SystemC (v2.3.3) support
  • Icarus Verilog (v10.3)

And upgrades the following development tools:

  • GCC (v8.3.1 from RHSCL)
  • Git (v2.9.3 from RHSCL)

Have an account?