Synopsys® provides a comprehensive portfolio of tools for digital and mixed-signal IC design, implementation, signoff, verification, test, and design for manufacturability. The following Synopsys software products and license counts are available for TSS beta evaluation.

Synopsys ZeBu

Synopsys ZeBu® emulation system delivers the performance needed to make verification teams and software developers working on the most advanced chips successful.

Siemens OneSpin

OneSpin provides solutions for design, synthesis and module verification and fault analysis for functional safety.

GNOME Desktop

GNOME is a desktop environment composed of free and open-source software that runs on Linux and most BSD derivatives. 

RISC-V Tools

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.

Real Intent

Real Intent® provides intent-driven static signoff tools to accelerate early functional verification of digital designs, leading the industry in precision, performance, and capacity.

Synopsys - Pilot Activity

Synopsys is an EDA tool. 

Synopsys - Training

A Synopsys installation for training

Cadence CPG

Custom IC & PCB Group

Cadence DSG

Cadence Digital Design & Signoff Group

Cadence SVG + Xilinx Vivado (RHEL 8)

Cadence System & Verification Group With Xilinx Vivado 2022.2

Cadence SVG + Xilinx Vivado (RHEL7)

Cadence System & Verification Group With Xilinx Vivado 2022.2 (RHEL7)

AMD Xilinx Vivado Design Suite

Vivado Design Suite is a software suite for synthesis and analysis of hardware description language designs, superseding Xilinx ISE with additional features for system on a chip development and high-level synthesis.

Graf Research + Xilinx Vivado

Enverite® PV-Bit™ verification allows users FPGA bitstream implementation to matches that of the publicly documented and post place-and-route (PAR) simulation netlist while Enverite® Trace™ archiver creates and verifies a tamper-evident auditable digital thread. With Xilinx Vivado 2020 and 2021 versions.

Cadence Palladium Z1 Compilation Pipeline

A pipeline that compiles a device for emulation

Cadence Palladium Z1 Emulation Pipeline

A pipeline that emulates a compiled runtime for a device

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